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Intel Requests Equal Application of Proposed Domestic Production Deduction Regs

APR. 3, 2006

Intel Requests Equal Application of Proposed Domestic Production Deduction Regs

DATED APR. 3, 2006
DOCUMENT ATTRIBUTES

Manousos, George

 

 

From: Palmintere, Nanci S [ nanci.s.palmintere@intel.com ]

 

Sent: Tuesday, April 04, 2006 12:18 PM

 

To: heather.c.maloy@irs.gov;

 

george.manousos@do.treas.gov

 

Subject: Letter on IRC 199

 

 

Dear Mr. Manousos and Ms. Maloy,

Attached is a letter from Intel on IRC section 199.

Sincerely,

 

 

Nanci S. Palmintere

 

Vice President, Finance and

 

Enterprise Services

 

Director, Global Tax and Trade

 

Intel Corporation

 

408-765-1190

 

nanci.s.palmintere@intel.com

 

April 3, 2006

 

 

Heather C. Maloy

 

Associate Chief Counsel (Passthroughs & Special Industries)

 

Internal Revenue Service (CC:P&SI)

 

1111 Constitution Avenue, N.W.

 

Washington, D.C. 20224

 

 

George M. Manousos

 

Office of Tax Legislative Counsel

 

United States Department of the Treasury

 

1500 Pennsylvania Avenue, N.W.

 

Washington, DC 20220

 

 

RE: Comments on Proposed Regulations Under IRC § 199 -- Application of IRC § 199 to Semiconductor Production Joint Ventures [Reg-105847-05]

Dear Ms. Maloy and Mr. Manousos:

I appreciate the opportunity to provide you with comments regarding the Proposed Treasury Regulations under IRC § 199 ("Proposed Regulations") and their application to semiconductor production joint ventures. Intel Corporation ("Intel") commends the Department of the Treasury ("Treasury") and the Internal Revenue Service for their efforts to provide prompt and comprehensive guidance with respect to IRC § 199. Intel is concerned, however, about the impact of Proposed Regulation § 1.199-5(g) on the U.S. semiconductor industry, in which joint ventures are utilized to share the high cost (up to $3 billion) of building and equipping production facilities. The purpose of this letter is to request that Treasury revise the Proposed Regulations to permit a domestic semiconductor company that is a partner in a U.S. joint venture engaged in the production of semiconductor products to obtain the deduction permitted by § 199 under the circumstances described below. We believe that it could not have been the intent of Congress to grant § 199 benefits to production partnerships in one industry but to deny them to economically equivalent partnerships, whether in the same industry or in other industries.

Overview of Fab Manufacturing in the Semiconductor Industry

Integrated circuits are silicon chips, known as semiconductors or "Die," etched with interconnected electronic switches. Intel manufactures its Die at wafer fabrication facilities ("fabs").1 For manufacturing efficiency, the Die are built on thin, round slices of silicon called "wafers." Surrounding each Die on the wafer are areas of silicon left largely "blank" to permit the Die to be separated from the wafer after fabrication. The fabrication process uses layering, patterning, and doping procedures to process a raw silicon wafer to the point of containing functional and/or operational integrated circuits. Once the fabrication process is completed, the Die undergoes a sorting process known as "Sort" to determine whether it meets acceptable performance criteria.

Overview of Assembly and Test in the Semiconductor Industry

After the Die are manufactured in the fab and Sort has been completed, the wafers with the finished Die are shipped to an assembly and test facility. "Assembly" refers to the series of operations after fabrication through which each Die that meets the required performance criteria is detached from the wafer and is attached to a piece of material that serves as a package. The assembly process consists of preparing the Die for attachment by separating the individual Die on the wafer, attaching the finished product to a purchased package, and then cleaning and drying the assembled product before testing.

The test process consists of operators loading assembled products into "burn-in" ovens, which subject the units to extreme thermal and voltage conditions in order to test their performance. After exposure to such conditions, operators load units into functional testers, then mark the assembled and tested products with an Intel logo and part information to complete the process. Intel then sells the assembled and tested product to customers worldwide through its sales and marketing activities.

Description of the Intel/Micron Joint Venture

In January 2006, Intel and Micron Technologies ("Micron") formed a joint venture ("JV") with operations in several states to produce NAND memory products. Intel and Micron did so to enter the fast-growing NAND memory market as quickly as possible. Micron not only possessed rights to the key intellectual property required for the production of NAND product, but also operated wafer fabrication plants, and Intel possessed the financial resources that would allow Micron to quickly re-tool and otherwise prepare the fabs to produce NAND products. By combining resources, Intel and Micron are able to enter the NAND market more quickly than they would have been able to do individually.

The JV uses the wafer fabrication process, described above, to embed a raw silicon wafer with functional and/or operational NAND flash memory Die, which are sorted based on acceptable performance criteria. After fabrication and Sort, the JV generally subcontracts the assembly and test functions, then transfers the assembled and tested products to Intel and Micron at the JV's book cost in proportion to their respective JV equity positions (adjusted from time to time based on a formula related to their relative economic interests in the JV). Intel and Micron are required either to purchase their proportionate shares of the JV's output or to reimburse the JV for their proportionate shares of the JV's unrecovered operating costs. Intel and Micron thus bear all of the economic risks of the JV's operations, while the JV bears no economic risks.

The JV conducts no sales or marketing activities. Instead, all sales and marketing activities for NAND products produced by the JV are conducted independently by Intel and Micron, which compete with each other to sell in their own names the NAND products they obtain from the JV. In considering alternative mechanisms for funding JV operating costs, Intel and Micron settled on a transfer-at-cost model, rather than a distribution-in-kind model coupled with periodic cost reimbursements, because potentially significant modifications to existing financial and logistics systems would have been required to accommodate a distribution-in-kind model. However, in terms of the rights and obligations of the parties, the economic consequences of both models are identical. In the case of the transfer-at-cost model, the JV recovers its operating costs (and only its costs) as and when products are transferred to the partners in proportion to their JV equity interests. In the case of the distribution-in-kind model, the JV periodically recovers its operating costs from the partners in proportion to their JV equity interests. The end result of this transfer-at-cost arrangement is the same as if (1) the JV transferred the assembled and tested product to Intel and Micron as a distribution with respect to their interests in the JV and (2) Intel and Micron periodically reimbursed the JV for their respective shares of the JV's operating expenses, as practiced by distribution-in-kind partnerships in the oil and gas industry. The JV, therefore, acts solely as a vehicle to allow Intel and Micron to pool their resources and share the cost of producing NAND products in proportion to their respective ownership interests in the JV.

The activities of the JV are clearly of the type for which a deduction under IRC § 199 is allowed, as intended by Congress. As currently drafted, however, the Proposed Regulations would prevent Intel and Micron from claiming the IRC § 199 deduction on the profits from their sales of products produced by the JV.

Intel's Recommendations for Changes to the Proposed Regulations

Intel is concerned about the impact on the U.S. semiconductor industry of Proposed Regulation § 1.199-5(g), which generally provides that, except with respect to certain oil and gas partnerships and affiliated group partnerships, the owner of a pass-thru entity is not treated as conducting the qualified production activities of the pass-thru entity. As currently drafted, this regulation would deny the § 199 deduction to semiconductor companies, such as Intel and Micron, merely because they choose to share the high cost of constructing and operating semiconductor production facilities in the U.S., contrary to the intent of Congress in enacting § 199. If Intel and Micron had each established its own independent domestic production facility, the § 199 deduction would clearly be available to both companies. Inasmuch as it is well recognized that semiconductor production requires enormous capital investments that few companies can make on their own, it is difficult to accept that, in designing a domestic production tax incentive, Congress intended to exclude joint production ventures in the semiconductor industry.

Intel believes this inequity can and should be addressed in the final regulations. The attribution exception for distribution-in-kind oil and gas partnerships of Proposed Regulation § 1.199-3(h)(7) should also apply to semiconductor production partnerships that conduct no sales or marketing activities and that transfer their output to partners in proportion to their ownership interests and in consideration for their respective shares of the JV's costs.

Expansion of the Oil and Gas Partnership Exception to Certain Semiconductor Production Partnerships

The exception of Proposed Regulation § 1.199-3(h)(7) should at least be extended to apply to partnerships that engage in semiconductor production, conduct no sales or marketing activities and sell or transfer products to their partners at book cost, such that the partners, rather than the partnership, report all of the taxable operating income attributable to the production and sale of semiconductor products. This change is appropriate for two reasons. First, such transfer-at-cost partnerships are economically equivalent to distribution-in-kind partnerships. In the former case, the JV is funded with payments made in connection with product flows, and in the latter case with capital calls or other periodic cost reimbursement mechanism. Semiconductor partners that acquire products at book cost reimburse the JV for its production costs on a per-unit basis as and when semiconductor products are transferred to the partners. The per-unit payments made by partners are nothing more than cost reimbursements. Second, like the oil and gas industry, semiconductor companies share the high cost of production through joint ventures and compete head-to-head in sales. In both industry models, the participants share the costs of production but not the profits or losses on sales of finished product.

Legacy systems and logistics drive semiconductor production JV's to transfer products to their partners by means of invoiced product transactions, rather than distributions in kind. The systems architectures of semiconductor companies are dependent on product sale invoices, which are required to move tangible products across international borders. To implement a distribution-in-kind model for a semiconductor production JV would require each partner to make significant systems modifications and/or adopt substantial and expensive manual processes. Therefore, when two semiconductor companies pool their resources, they necessarily extend their systems architectures to their JV's and to the products acquired from those JV's.

Intel understands that Treasury and the Internal Revenue Service need to clearly identify those partnerships that are excepted from the prohibition on partnership attribution and those partnerships that are not. An exception could be specifically provided for semiconductor companies, which pool their resources to construct and operate very high-cost U.S. production facilities through joint ventures that are economically equivalent to the distribution-in-kind partnerships in the oil and gas industry. Under the current proposed regulations, the U.S. semiconductor industry will suffer the loss of § 199 benefits unless semiconductor companies operate independently (which may be cost ineffective and, therefore, noncompetitive).

Conclusion

For the foregoing reasons, Intel respectfully requests that, when finalized, the § 199 regulations include an exception for semiconductor production partnerships that are engaged solely in production, conduct no sales or marketing activities and transfer product to their partners at book cost, (such that the partners, rather than the partnership, recognize all of the taxable operating income attributable to the production and sale of semiconductor products). For your convenience, proposed regulatory language to this effect is provided in Appendix A, attached.

Please call me at (408) 765-1190 if you have any questions. I appreciate your consideration of this issue.

Respectfully Submitted,

 

 

Nanci S. Palmintere

 

Vice President and Director,

 

Global Tax and Trade

 

cc: Eric Solomon, Acting Assistant Secretary (Tax Policy)

 

 

Donald Korb, Chief Counsel of the Internal Revenue Service

 

FOOTNOTE

 

 

1 Most of Intel's wafer fabrication facilities are in the U.S. Intel also has wafer fabs in Ireland and Israel.

 

END OF FOOTNOTE

 

 

APPENDIX A

 

 

(9) Exception for certain semiconductor production partnerships -- (i) In general. If a partnership is engaged solely in the production of semiconductor products, and in proportion to the partners' ownership interests in the partnership, the partnership sells or otherwise transfers the semiconductor products to its partners at the partnership's book cost, or the partnership is otherwise reimbursed for its production costs by the partners in the same proportions, then each partner is treated as producing semiconductor products transferred to that partner. Thus, to the extent that the production of the transferred products occurs in whole or in significant part within the United States, gross receipts derived by each partner from the sale, exchange, or other disposition of the transferred semiconductor products are treated as DPGR (provided all requirements of this section are met). Solely for purposes of section 199(d)(1)(A)(iii)(II), the partnership is treated as having gross receipts in the taxable year of the transfer equal to the fair market value of the transferred semiconductor products at the time of transfer to the partner, and the deemed gross receipts are allocated to that partner, provided the partner derives gross receipts from the transferred property during the taxable year of the partner with or within which the partnership's taxable year (in which the transfer occurs) ends. Costs included in the adjusted basis of the transferred semiconductor products and any other relevant deductions are taken into account in computing the partner's QPAI. See § 1.199-5 for the application of section 199 to pass-thru entities.

(ii) Example. The following example illustrates the application of this paragraph (h)(9). Assume that PRS and X are calendar year taxpayers. The example reads as follows:

Example. X is a partner in PRS, a partnership that engages solely in the production of semiconductor products within the United States. In 2010, PRS sells or otherwise transfers to X for its book cost semiconductor products produced by PRS. PRS incurred $600 of CGS, including $500 of W-2 wages (as defined in § 1.199-2(f)), producing the semiconductor products transferred to X, and X's adjusted basis in the transferred semiconductor products is $600. The fair market value of the transferred products at the time of transfer to X is $1,000. In 2010, X sells the semiconductor products for $900 to a customer. Under paragraph (h)(9)(i) of this section, X is treated as having produced the semiconductor products. The production of the semiconductor products is an MPGE activity under paragraph (d)(1) of this section. Therefore, X's $900 of gross receipts qualify as DPGR. X subtracts from the $900 of DPGR the $600 of CGS incurred by PRS. Thus, X's QPAI is $300 for 2010. In addition, PRS is treated as having $ 1,000 of DPGR solely for purposes of applying the wage limitation of section 199(d)(1)(A)(iii)(Il). Accordingly, X's share of PRS's W-2 wages determined under 199(d)(1)(A)(iii)(II) is $72, the lesser of $500 (X's allocable share of PRS's W-2 wages included in CGS) and $72 (2 x ($400 ($1,000 deemed DPGR less $600 of CGS) x 0.09)).

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